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Ordering number : ENA1337
LC01700PW
Overview
CMOS LSI
FM tuner IC for VICS
LC01700PW is an FM tuner IC for vehicle-mounted VICS incorporating FM FE, IF, OP AMP, PLL. VICS tuner can be developed by one chip. This IC can make up a small FM tuner module mounted for navigation.
Features
* Dedicated FM tuner IC for VICS in Japan and RDS in Europe. * Variable gain LNA incorporated. * A pulse counter detection method employed in the FM detection circuit. No adjustment necessary. * Less number of external parts. * BUS control tuner IC enabling control with I2C BUS. * OP AMP provided to adjust the composite frequency level appropriate to VICS and RDS. * 6Bit-ADC incorporated to enable digital output of S meter.
Functions
* FM-FE+IF+OP AMP+PLL
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VDD H VDD L Pd max Topr Tstg Ta 85C Conditions Ratings 6 6 6 400 -40 to +85 -50 to +150 Unit V V V mW C C
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
O1508 MS PC 20080924-S00001 No.A1337-1/18
LC01700PW
Operating supply voltage range at Ta = 25C
Parameter Recommended supply voltage Supply voltage range Symbol VDD VDD Conditions Not to exceed the absolute maximum rating Ratings 4.5 to 5.5 5.0 Unit V V
Serial interface voltage level
Parameter High level input voltage Low level input voltage High level output voltage (opendrain) Low level output voltage (open*drain) * High level output voltage causes the open drain to become the high-impedance state. Since the drain is pulled up to VDD, the voltage is equal to VDD. VOL 0.0 Symbol VIH VIL VOH Conditions min 2.4 0.0
VDD : Communications bus voltage Ratings typ max VDD 0.7 VDD* 0.2VDD V V V V Unit
Electrical Characteristics at Ta = 25C, unless otherwise specified. fc = 83MHz, Vin = 60dBVEMF, fm = 1kHz, Audio filter : HPF =100Hz, LPF = 15kHz Sample application circuit (Sample application circuit) look-up Register map look-up
Parameter S/N 30dB sensitivity S/N 10dB sensitivity *1 Seek sensitivity (LO) Symbol SN30 SN10 Seek Conditions min 22.5kHz dev, fm = 1kHz, S/N = 30dB input level 7.5kHz dev, fm = 76kHz, S/N = 10dB input level *2 22.5kHz dev, Vin = 40dBVEMF Vsm = 2.0V adjustment Pin 18 (STDO) Lo Hi input level S/N ratio 1 S/N ratio 2 Total harmonic distortion 1 Total harmonic distortion 2 Total harmonic distortion 3 Image removal ratio AM suppression ratio Audio output level 1 Audio output level 2 Current drain *1 S/N = 10dB at BER = 1% *2 Audio filter : HPF = 100Hz, LPF = OFF SN_1 SN_2 THD_1 THD_2 THD_3 Image AMR Vo_1 Vo_2 IDD 22.5kHz dev, fm = 1kHz 7.5kHz dev, fm = 76kHz *2 22.5kHz dev, fm = 1kHz 75.0kHz dev, fm = 1kHz 22.5kHz dev, fm = 1kHz, Vin = 120dBVEMF 22.5kHz dev, fm = 1kHz AM 30% mod 75.0kHz dev, fm = 1kHz 7.5kHz dev, fm = 76kHz *2 Input at no signal 40 45 170 16 50 60 35 0.1 0.2 0.1 50 55 270 25 30 430 40 45 1 1 1 dB dB % % % dB dB mVrms mVrms mA 15 Ratings typ 15 25 22 29 max 20 dBVEMF dBVEMF dBVEMF Unit
No.A1337-2/18
LC01700PW
Package Dimensions
unit : mm (typ) 3163B
9.0 7.0 36 37 25 24
48 1 0.5 (0.75) 12 0.18
13
7.0 9.0
0.15
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
0.5
No.A1337-3/18
LC01700PW
Sample Application Circuit (Block Diagram)
COMPOUT
SMETER
0.1F R2( 4) C( 6) * *
1F 0.1F
18pF
10F
R3(*5)
3300pF GND_IF
500k
REG 10F
0.1F 47k
82pF
36 35 34
33
32
31 30 29 28 27 26
25 24
0.1F VDD_IO 8pF X(*7) 8pF
Demod
OPAMP
23 VSS 22
3V REG
IF CNT
IRSSI
SMUTE
21
BUFF
POR
1shot 1.8V REF
20
IOBUS
37 38 0.1F 39 40
ADC
SCL 1k SDA 1k STDO 10k
19 18
41 1F VDD_IF 0.1F 1F 45 VDD_AGC 46 0.1F 1F 47 48 42
SD COMP
I/F
CF(*3)
Ref. Counter
1.5V
17 16
Level Shift
43 44
Prog. Counter
Lock Det.
Charge Pump
AGC COMP
SMUT E CNT
Phase Det.
Keyed-AGC
0.1F 15 5.6k 1F
SVC720
RF AGC
W-AGC
N-AGC
14 13
180nH 3pF
180nH 100k
1
100pF
2
100pF
34 0.1F 110nH 0.1F
56
SVC720
7
VDD - RF 1000pF
8
22pF 2pF 22pF
9
10
SVC720 GND - RF
11
GND - LO
12 1F
VDD - LO
CF(*3)
10pF
110nH T2(*1)
100k
100k 0.1F
R1(*2)
0.1F
T1(*1) 1000pF
220
0.1F 33 1SV249
12pF 100nH
56pF RF - IN
(*1) T1 -TOKO : 5CCE #A638AN -1840YFZ T2 -TOKO : 5CCL ##613BG -0581WN (*2) R1 -TAIYO YUDEN: BK1608HS102 -T (*3) CF -MURATA : SFELL15M0GQQTS01 -B0 3dB Bandwidth 230 50kHz
22pF
(*6) C -fm = 1kHz : NM fm = 76kHz : 680pF (*7) X -NIHON DENPA KOGYO CO.,LTD : AT41 14.55MHz
(*4) R2 -fm = 1kHz : NM fm = 76kHz : 6.8k (*5) R3 -fm = 1kHz : 0 m = 76kHz : 6.8k
No.A1337-4/18
LC01700PW
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name MIX_ON MIX_OP MIX_IP MIX_IN LNA_ON LNA_OP VDD_RF FM_IP FM_IN GND_RF GND_LO VDD_LO LOSC2 LOSC1 VT NC1 NC2 STDO SDA SCL XOSC2 XOSC1 VSS VDD_IO VDD GND_IF COMPOUT DETREF DETADJ DETINP DETINN FDO SMETER CRSSI LIM2 LIM1 NC3 NC4 IF2nd_IN IF2nd_IP IF1stOUT VDD_IF IF1st_IN IF1st_IP VDD_AGC FMAGC CAGC LNAAGC Type OUT OUT IN IN OUT OUT POWER IN IN GND GND POWER IN/OUT IN/OUT OUT NC NC OUT IN/OUT IN IN/OUT IN/OUT GND POWER OUT GND OUT IN/OUT OUT IN IN OUT IN/OUT IN/OUT IN/OUT IN/OUT NC NC IN IN OUT POWER IN IN POWER OUT IN/OUT IN/OUT 1stMIX signal output (-) 1stMIX signal output (+) 1stMIX signal input (+) 1stMIX signal input (-) LNA signal output (-) LNA signal output (+) RF block power FM signal input (+) FM signal input (-) RF block GND LO block GND LO block power VCO resonant load pin 2 VCO resonant load pin 1 Charge pump output NC NC Monitor output/reset detection output Serial data I/O (I2C) Serial clock input (I2C) Crystal oscillator pin 2 Crystal oscillator pin 1 Digital block GND 5V power for interface Digital block power (built-in regulator output) IF block GND Composite signal output FM detection signal amplifier reference voltage FM detection signal amplitude adjustment FM detection signal amplifier input (+) FM detection signal amplifier input (-) FM detection circuit output S meter output Connection of smoothing capacitor for S-meter/S-meter output voltage adjustment Limiter offset canceling capacitor connection 2 Limiter offset canceling capacitor connection 1 NC NC 2ndMIX signal input (-) 2ndMIX signal input (+) 1st IF amplifier signal output IF block power 1st IF amplifier signal input (-) 1st IF amplifier signal input (+) Pin diode AGC circuit power FM pin diode driver output AGC circuit smoothing capacitor connection 2 AGC circuit smoothing capacitor connection 1 Description
No.A1337-5/18
LC01700PW
Communications Specifications
Communications specifications are shown below : Serial Interface(I2C-bus) ; Serial interface (I2C-bus) Send/receive is made via I2C-bus that consists of two bus lines, each being a serial * data * line (SDA) and serial * clock * line (SCL). This bus enables 8-bit bi-directional serial data transmission at maximum 400kbit/s (fast mode). This is not compatible with the Hs mode. 1. Terms used in I2C The following terms are used in I2C.
Terms Transmitter Receiver Master Slave Device to send data to the bus Device to receive data from the bus Device to start data transmission, to generate the clock signal, and to end data transmission Device whose address is designated by the master Description
2. "Start" and "Stop" conditions "Start" condition must be satisfied at start of data communications and "Stop" condition must be satisfied at end of communications. The condition in which the SDA line changes from "H" to "L" with SCL at "H" is called the "Start" line. The condition in which the SDA line changes from "L" to "H" with SCL at "H" is called the "Stop" condition.
SDA
SDA
SCL S START condition P STOP condition
SCL
No.A1337-6/18
LC01700PW
3. Data transmission The length of each byte output to the SDA line is always 8 bits. An acknowledge bit is always necessary after each byte, Data is transmitted sequentially from the most significant bit (MSB). During data transfer, the slave address is transmitted after the "Start" condition (S). Data transfer is always ended by the "Stop" condition (P) generated by the master.
ACK ; acknowledgement ACK signal from slsave D6 D1 D0 Sr byte complete, interrupt within slave clock line held low while interrupts are serviced SCL S or Sr 1 2 7 8 9 1 2 3-8 9 Sr or P STOP or repeated START condition ACK signal from receiver P SDA D7 Mostsignificant bit of MSB
START or repeated START condition
clock pulse for ACK
clock pulse for ACK
4. Acknowledge (Confirmation of reception) When the master generates the acknowledge clock pulse, the transmitter opens the SDA line (SDA line entering the "H" state). When the acknowledge clock pulse is in the "H" state, the receiver sets the SDA line to "L" each time it receives one byte (eight bits) of data. When the master functions as receiver, the master informs the end of data to the slave by omitting acknowledgement at the end of data sent from the slave.
Release the SDA line(HIGH) Dataoutput by Transmitter
NACK(master is reciever) Dataoutput by Receiver ACK(master is transmitter) SCL from Master S START condition ACK ; acknowledgement NACK ; not acknowledgement clock pulse for ACK
1
2
8
9
No.A1337-7/18
LC01700PW
5. Software reset After power ON, enter the signal as follows to avoid malfunction. If the communication is interrupted (microcomputer reset, etc.), entry of the following signal enables normal operation.
SDA
SCL S 1 2 7 8 9 Sr P
START condition
reperted START condition
STOP condition
6. Electrical Specification and Timing for I/O Stages
t1
t2
SDA t4 SCL t10 t5 START condition t6 t3 t8 STOP condition t2 t7 t1 t9
Bus line characteristics
FAST-MODE Parameter SCL clock frequency SDA, SCL fall time SDA, SCL rise time SCL "H" time SCL "L" time "Start" condition hold time Data hold time For I2C bus device Data setup time "Stop" condition setup time "Stop"-"Start" bus free time "Start" condition setup time Bus line capacitive load Symbol min fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Cb 20+0.1Cb 20+0.1Cb 0.6 1.3 0.6 0.3 0.1 0.6 1.3 0.6 max 400 300 300 400 kHz ns ns s s s s s s s s pF unit For SCL = 100kHz (Example) 100 3 7 10 3 10 20 -
No.A1337-8/18
LC01700PW
7. Definition of each bit in one byte 7-1. Slave address The slave address consists of a fixed seven-bit address "1110010" uniqueto the chip and the eighth bit or a data direction bit (R/W) : Send (Write) when this bit is "0" and Receive (Read) when this bit is "1".
7-2. Register address Since the total number of internal registers is 16, 4-bit data set on the MSB side becomes invalid.
7-3. Register data Each register data consists of eight bits.
MSB
1 1 1 0 0 1 0 Fixed address
R/W
R/W READ WRITE BIT 1 0
LSB
MSB
0 0 0 0 A3 A2 A1 Invalid address Valid address
LSB
A0
MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0
No.A1337-9/18
LC01700PW
8. Command Format 8-1. Individual register * data writing
Write Invalid address
SDA
S
1
1
1
0
0
1
0
0
0
0
0
0
0
1/0 1/0 1/0 1/0
0
START condition
Slave address
ACK
Register address
ACK
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
P
Register data From master to slave
ACK STOP condition From slave to master
8-2. Individual register * data reading
Write Invalid address
SDA
S
1
1
1
0
0
1
0
0
0
0
0
0
0
1/0 1/0 1/0 1/0
0
START condition
Slave address Read
ACK
Register address
ACK
Sr
1
1
1
0
0
1
0
1
0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
1
P
Repeated START condition
Slave address
ACK From slave to master
Register address
NACK STOP condition
From master to slave
No.A1337-10/18
LC01700PW
8-3. Consecutive register * data writing
Write Invalid address
SDA
S
1
1
1
0
0
1
0
0
0
0
0
0
0
1/0 1/0 1/0 1/0
0
START condition
Slave address
ACK
Register address
ACK
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
Register data (of Register address)
ACK Register data (of Register address+1) ACK
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
0
P
Register data (of Register address+2) ACK Register data (of Register address+n) ACK STOP condition From master to slave From slave to master
Continuous data transmission after transmission of initially-set address data of register * data writing sequence enables writing of data in the consecutive register * data area. In this case, the register * address increases by one address from the initially-set address of the sequence and continues increasing till the "Stop" condition (P) is generated.
8-4. Consecutive register * data reading
Write Invalid address
SDA
S
1
1
1
0
0
1
0
0
0
0
0
0
0
1/0 1/0 1/0 1/0
0
START condition
Slave address Read
ACK
Register address
ACK
Sr
1
1
1
0
0
1
0
1
0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
Repeated START condition
Slave address
ACK
Register data (of Register address)
ACK
0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
0
1
P
ACK Register data (of Register address+1) ACK Register data (of Register address+n) NACK STOP condition From master to slave From slave to master
When the master returns ACK (0 data) after reading of the initial register * address * data of read sequence, the register * address increases by one address, enabling consecutive reading of data corresponding to each register address. If the master does not return ACK (0 data), the register address does not increase.
No.A1337-11/18
LC01700PW
Register Map
Register address 0 Bit 7 6 5 4 3 2 1 0 1 7 6 5 4 3 2 1 0 2 7 6 5 4 3 2 1 0 3 7 6 5 4 3 2 1 0 4 7 6 5 4 3 2 1 0 5 7 6 5 4 3 2 1 0 15:150A CI ChargePump output current setting RSEL ADCLK DZSEL PLL REF reference frequency selection RSSIADC clock frequency changeover Dead zone adjustment 0:50kHz 0:800kHz 0:0ns 2:10ns 0:0A *10A STEP 1:2ns 3:20ns 1 0 0 0 FSEL PLL comparative frequency setting CSEL PLL master clock signal selection GT 2ndIF count time selection 0:4ms 2:32ms 0:10.95MHz 2:14.55MHz 4:21.15MHz 0:50kHz 1:8ms 3:64ms 1:11.25MHz 3:14.75MHz 5:21.45MHz 0 2 0 CTE RSTDET PCNT 2ndIF count measurement start control Initial register writing for reset detection PLL synthesizer program data 0:OFF 0:Reset 0:LSB 55:50dBV (As for value reference value) 1:ON (automatically OFF) 1:Normal 0 1 SDREG LO/DX changeover (seek determination level adjustment) *1dB STEP 15:10dBV 15:Oscillation level large 25 LOBIAS Oscillation level adjustment Name PE SWSTD Functions Power enable (all blocks) Selection of digital signal monitor pin output /reset detection output 0:OFF 0:RSTDET 4:IFCNT_CLK 6:PROCNTR 0:Oscillation level small 1:SD * Register value : Decimal notation Bit operation 1:ON 2:LDO 5:RSSI_CLK 7:REFCNTR 0 3:KAGC Default value 1 1
PCNT =
Receiver frequency + 1stl frequency (upperlocal setting) 50kHz Receiver frequency + 1stl frequency (lowerlocal setting) 50kHz
PCNT =
Continued on next page.
No.A1337-12/18
LC01700PW
Continued from preceding page.
Register address 6 Bit 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 9 7 6 5 4 3 2 1 0 10 7 6 5 4 3 2 1 0 11 7 6 5 4 3 2 1 0 0:Fixing 0:Fixing 7:oscillation allowance, large 0 0 XOSCADJ Crystal oscillation level adjustment 0:oscillation allowance, small 0 IFAG 1stIFA gain adjustment MIXG 1stMIX gain adjustment WAGCSW NAGCSW ATTAGCSW LNAAGCSW KAGCSW WKAGCSW LNAG W_AGC_ON/OFF N_AGC_ON/OFF ATT_AGC_ON/OFF LNA_AGC_ON/OFF Keyed-AGC_ON/OFF Keyed-W_AGC sensitivity changeover LNA gain adjustment 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:No sensitivity change 0:17dB 2:21dB 0:-0.2dB 2:4.5dB 0:7dB 2:13dB 0:Fixing KAGC Keyed-AGC judgment level adjustment 0:-3dBV *2dB STEP 15:27dBV (As for value reference value) 1:ON 1:ON 1:ON 1:ON 1:ON 1:-10dB sensitivity change 1:19dB 3:23dB 1:2.8dB 3:5.4dB 1:10dB 3:16dB 0 3 3 1 1 1 1 0 0 3 15:Sensitivity high 6 NAGC N_AGC sensitivity adjustment 0:Sensitivity low 15:Sensitivity high *1.1dB STEP 6 WAGC W_AGC sensitivity adjustment 0:Sensitivity low *1.1dB STEP 15 0:Fixing RSSITMP RSSI detection temperature characteristics adjustment *Front-end circuit temperature characteristics compensation 0:4dB RSSIGAIN RSSI detection sensitivity adjustment *RSSI output gradient 0:31mV/dB SMTREG Softmute start point adjustment PEVCO BGRTEST Power enable (VCO) BGR (RFAGC circuit) inspection mode changeover Name Functions 0:Fixing 0:OFF 0:OFF 0:Fixing 0:Softmute function OFF 1:-4dBV *2dB STEP 15:24dBV (As for value reference value) *1mV/dB STEP 7:38mV/dB (As for value reference value) *0.5dB STEP 7:7.5dB (As for value reference value) 0 3 4 1:ON 1:ON * Register value : Decimal notation Bit operation Default value 0 1 0 0 10
Continued on next page.
No.A1337-13/18
LC01700PW
Continued from preceding page.
Register address 12 Bit 7 6 5 4 3 2 1 0 13 7 6 5 4 3 2 1 0 14 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 PERF PEIF PEDEM PEAMP PEXOSC PELNA PELO1 PELO2 PEREFCNT PERFAGC Power enable (RF block) Power enable (IF block) Power enable (LIM/DEMOD) Power enable (audio amplifier) Power enable (XOSC) Power enable (LNA) Power enable (LO block_VCOetc) Power enable (LO block_LOBUFetc) Power enable (REF counter) Power enable (RFAGC block) 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF DEMODR Detection output level adjustment 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 7 Name RMXG Functions Composite output level adjustment 0:3.1dB * Register value : Decimal notation Bit operation 1:3.7dB 2:4.4dB 3:5.2dB Default value 0
0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms (As for value reference value) 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON
1 1 1 1 1 1 1 1 1 1
No.A1337-14/18
LC01700PW
Register Map
Register address 0 Bit 7 6 5 4 3 2 1 0 1 7 6 5 4 3 2 1 0 2 7 6 5 4 3 2 1 0 3 7 6 5 4 3 2 1 0 4 7 6 5 4 3 2 1 0 5 7 6 5 4 3 2 1 0 15:150A CI ChargePump output current setting RSEL ADCLK DZSEL PLL REF reference frequency selection RSSIADC clock frequency changeover Dead zone adjustment 0:50kHz 0:800kHz 0:0ns 2:10ns 0:0A *10A STEP 1:2ns 3:20ns 1 0 0 0 FSEL PLL comparative frequency setting CSEL PLL master clock signal selection GT 2ndIF count time selection 0:4ms 2:32ms 0:10.95MHz 2:14.55MHz 4:21.15MHz 0:50kHz 1:8ms 3:64ms 1:11.25MHz 3:14.75MHz 5:21.45MHz 0 2 0 CTE RSTDET IFCOUT 2ndIF count measurement start control Initial register writing for reset detection 2ndIF count value output 0:OFF 0:Reset 0:LSB 55:50dBV (As for value reference value) 1:ON (automatically OFF) 1:Normal 0 1 SDREG LO/DX changeover (seek determination level adjustment) *1dB STEP 15:10dBV 15:Oscillation level large 25 LOBIAS GM adjustment of the oscillation circuit core block Name PE SWSTD Functions Power enable (all blocks) Selection of digital signal monitor pin output /reset detection output 0:OFF 0:RSTDET 4:IFCNT_CLK 6:PROCNTR 0:Oscillation level small 1:SD * Register value : Decimal notation Bit operation 1:ON 2:LDO 5:RSSI_CLK 7:REFCNTR 0 3:KAGC Default value 1 1
2ndIF frequency =
IFCOUT value (2ndIF count value) GT
Continued on next page.
No.A1337-15/18
LC01700PW
Continued from preceding page.
Register address 6 Bit 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 9 7 6 5 4 3 2 1 0 10 7 6 5 4 3 2 1 0 11 7 6 5 4 3 2 1 0 0:Fixing 0:Fixing 7:Oscillation allowance, larg 0 0 XOSCADJ Crystal oscillation level adjustment 0:oscillation allowance, small 0 IFAG 1stIFA gain adjustment MIXG 1stMIX gain adjustment WAGCSW NAGCSW ATTAGCSW LNAAGCSW KAGCSW WKAGCSW LNAG W_AGC_ON/OFF N_AGC_ON/OFF ATT_AGC_ON/OFF LNA_AGC_ON/OFF Keyed-AGC_ON/OFF Keyed-W_AGC sensitivity changeover LNA gain adjustment 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:No sensitivity change 0:17dB 2:21dB 0:0dB 2:4dB 0:7dB 2:13dB 0:Fixing KAGC Keyed-AGC judgment level adjustment 0:-3dBV *2dB STEP 15:27dBV (As for value reference value) 1:ON 1:ON 1:ON 1:ON 1:ON 1:-10dB sensitivity change 1:19dB 3:23dB 1:2dB 3:6dB 1:10dB 3:16dB 0 3 3 1 1 1 1 0 0 3 15:Sensitivity high 6 NAGC N_AGC sensitivity adjustment 0:Sensitivity low 15:Sensitivity high *1.1dB STEP 6 WAGC W_AGC sensitivity adjustment 0:Sensitivity low *1.1dB STEP 15 0:Fixing RSSITMP RSSI detection temperature characteristics adjustment *Front-end circuit temperature characteristics compensation 0:4dB RSSIGAIN RSSI detection sensitivity adjustment *RSSI output gradient 0:31mV/dB SMTREG Softmute start point adjustment PEVCO BGRTEST Power enable (VCO) BGR(RFAGC circuit) inspection mode changeover Name Functions 0:Fixing 0:OFF 0:OFF 0:Fixing 0:Softmute function OFF 1:-4dBV *2dB STEP 15:24dBV (As for value reference value) *1mV/dB STEP 7:38mV/dB (As for value reference value) *0.5dB STEP 7:7.5dB (As for value reference value) 0 3 4 1:ON 1:ON * Register value : Decimal notation Bit operation Default value 0 1 0 0 10
Continued on next page.
No.A1337-16/18
LC01700PW
Continued from preceding page.
Register address 12 Bit 7 6 5 4 3 2 1 0 13 7 6 5 4 3 2 1 0 14 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 RSSIOUT RSSI digital output 0:LSB SMTSWOUT Soft mute changeover control signal output 0:LSB PERF PEIF PEDEM PEAMP PEXOSC PELNA PELO1 PELO2 PEREFCNT PERFAGC WAGCOUT Power enable (RF block) Power enable (IF block) Power enable (LIM/DEMOD) Power enable (audio amplifier) Power enable (XOSC) Power enable (LNA) Power enable (LO block_VCOetc) Power enable (LO block_LOBUFetc) Power enable (REF counter) Power enable (RFAGC block) W_AGC output 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:LSB DEMODR Detection output level adjustment 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 7 Name RMXG Functions Composite output level adjustment 0:3.1dB * Register value : Decimal notation Bit operation 1:3.7dB 2:4.4dB 3:5.2dB Default value 0
0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms (As for value reference value) 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON 1:ON
1 1 1 1 1 1 1 1 1 1
No.A1337-17/18
LC01700PW
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of October, 2008. Specifications and information herein are subject to change without notice. PS No.A1337-18/18

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